Using a parallel electrical bus, digital signals that represent symbols can be propagated between drivers and receivers. A symbol, as discussed herein, represents a single unit of data, representing a binary 0 or 1 that is transmitted on a single wire on a bus. In a source-synchronous clocking configuration, each symbol is also accompanied by a source-synchronous clock or strobe that is transmitted on a separate wire. The clock or strobe provides a timing reference to the receiver for sampling the symbol value. In prior systems, a single clock or strobe provides a timing reference for many data wires on the parallel bus. The receiver must sample a value of the data from the bus during a timing eye, which is a period when the data is known to be valid. The timing relationship between the timing eye and the received strobe or clock may be adversely affected by factors that degrade signal integrity. For example, factors may include reflections resulting from mis-termination or stubs, over-dampening resulting from weak drivers, weak or delayed signal drive resulting from simultaneous switching of multiple drivers, and the like. Degradation of this timing relationship may reduce the reliability of the bus or may lower the achievable performance by forcing a chip designer to adopt a lower symbol rate in order to widen the timing eye.
The term “inter-symbol interference” applies to a specific subset of factors that degrade signal integrity. It applies to factors that are correlated with the history of symbols recently carried on the same bus line. For example, on an over-damped bus, a wire that switches from a low value to a high value at the beginning of a symbol interval, may not reach as high a signal level by the beginning of the next signal interval, as compared to a second wire that has been continuously high all along. If both wires subsequently transition to a low value, the wire that has been continuously high will be further from its switching threshold than the wire that has only recently switched to the high value. If the wires have similar slew rates, the latter will be seen to switch low earlier than the former. More complicated inter-symbol interference patterns can occur if the bus topology contains stubs or mis-terminations such that energy from one switching transition is still present in the form of a reflection two or even more symbol intervals later.
One technique that has been used to compensate for inter-symbol interference is known as driver pre-compensation. In this technique, a circuit driving each line of a data bus keeps track of the symbol history of each line. Based upon the history of the prior symbols driven, the circuit varies some characteristic of the driver, such as the drive strength, edge rate, or possibly timing of switching. The variation is done in such a way as to compensate the timing of the symbol's timing eye as it is expected to be seen by the receiver such that the relative timing of the signal eye and the clock or strobe is closer to nominal than it would be without pre-compensation. Correct implementation and use of pre-compensation requires careful modeling of the driver, the transmission line, and the receiver to accurately predict the effect of symbol history on the signal timing eye.